Transistor structure and related transistor packaging method thereof

ABSTRACT

A transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. provisional application No.61/533,796 (filed on Sep. 13, 2011) and U.S. provisional application No.61/682,319 (filed on Aug. 13, 2012). The entire contents of the relatedapplications are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a transistor structure and transistorpackaging method thereof, and more particularly, to a transistorstructure with two pins and related packaging method thereof.

2. Description of the Prior Art

In recent years, due to the continued development of the technology ofelectronic circuits, the protection circuits of a variety ofelectrical/electronic components are widely implemented in manyapplications. In conventional protection circuits, for instance, a RCDsnubber circuit 400 as shown in FIG. 19 is formed by making the resisterR6 and the capacitor C12 connected in parallel, and then connected tothe diode D11 in series. However, the RCD snubber circuit hasdisadvantages like the high energy loss, poor efficiency and high spikevoltage value, so the use of conventional RCD snubber circuit couldeasily lead to the damage of the semiconductor elements. Therefore,there is a need for a novel electronic component which may replace diodeD11 to enhance the circuit protection performance of the snubbercircuit.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a transistorstructure and a related packaging method, which may be applied to asnubber circuit to protect components efficiently and improveefficiency.

An objective of the present invention is to provide a transistorstructure and the related packaging method, which can simplify theprocess, reduce size, and increase the withstanding voltage.

To achieve the aforesaid objectives, the transistor structure of thepresent invention includes a chip package and two pins, wherein the chippackage includes a transistor die and a molding compound encapsulatingthe transistor die; and a first pin of the pins is electricallyconnected to a first and a second bonding pads of the transistor die,and a second pin of the pins is electrically connected to a thirdbonding pad of the transistor die.

In accordance with the aforesaid transistor structure, the first pin orthe second pin of the transistor structure is connected to a terminal ofa capacitor, thereby forming a snubber circuit to be connected to anactive component or a load in parallel.

In accordance with the aforesaid transistor structure, one terminal ofthe capacitor is further connected to one terminal of a zener diode, andanother terminal of the capacitor is connected to another terminal ofthe zener diode, thereby forming a snubber circuit to be connected to anactive component or a load in parallel.

In accordance with the aforesaid transistor structure, the first pin orthe second pin is connected to a terminal of a resistor, and anotherterminal of the resistor is connected to a terminal of a capacitor,thereby forming a snubber circuit to be connected to an active componentor a load in parallel.

In accordance with the aforesaid transistor structure, the activecomponent is or is assembled by a Metal Oxide Semiconductor Field EffectTransistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), anInsulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor(SIT), or a thyristor, and the load is or is assembled by an inductor, aresistor, or a capacitor.

In accordance with the aforesaid transistor structure, the transistordie is a BJT die.

In accordance with the aforesaid transistor structure, the first bondingpad of the transistor die is an emitter bonding pad, and the secondbonding pad is a base bonding pad, and the third bonding pad is acollector bonding pad.

In accordance with the aforesaid transistor structure, the first bondingpad, the second bonding pad, and the third bonding pad is connected tothe pins by way of wire bonding.

In accordance with the aforesaid transistor structure, the wire bondingis connected to the pins through three bonding wires respectively.

In accordance with the aforesaid transistor structure, the first bondingpad and the second bonding pad are electrically connected to each other,and one of the pins is connected to the first bonding pad or the secondbonding pad through a bonding wire, and the third bonding pad isconnected to another one of the pins through a bonding wire.

In accordance with the aforesaid transistor structure, the first bondingpad, the second bonding pad, and the third bonding pad are electricallyconnected to the pins by way of flip chip bonding.

In accordance with the aforesaid transistor structure, the chip packagefurther comprises a die pad, and the transistor die is set on the diepad by an adhesion layer.

Therefore, one of the pins is electrically connected to a first bondingpad and a second bonding pad of the transistor die, and another one ofthe pins is electrically connected to a third bonding pad of thetransistor die. The transistor structure may be applied in a snubbercircuit, or the snubber circuit may be encapsulated in the two-pintransistor structure to connect an active component or a load inparallel to absorb spikes or noise generated by the active componentwhile the active component is switching at a high frequency. Therefore,the packaging of the transistor structure could simplify the process,reduce size, increase the withstanding voltage, and improve theefficiency and reduce the spike voltage of the power supply of thesnubber circuit.

It should be noted that the aforesaid general descriptions and thefollowing embodiments are only for illustrative purposes, and do notlimit the scope of the present invention.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram illustrating a transistor structure according to afirst embodiment of the present invention.

FIG. 1B is a diagram illustrating a transistor structure according to asecond embodiment of the present invention.

FIG. 1C is a diagram illustrating a transistor structure according to athird embodiment of the present invention.

FIG. 2A is a diagram illustrating a transistor die of the presentinvention which is a BJT die.

FIG. 2B is a diagram illustrating a transistor die of the presentinvention which is a BJT die.

FIG. 2C is a diagram illustrating a connection between a BJT die and acapacitor die of the present invention.

FIG. 2D is a diagram illustrating a connection between a BJT die, acapacitor die, and a zener diode of the present invention.

FIG. 3 is a sectional diagram illustrating the transistor structureelectrically connected to pins and bonding pads by way of wire bondingaccording to an embodiment of the present invention.

FIG. 4 is a sectional diagram illustrating the transistor structureelectrically connected to pins and bonding pads by way of wire bondingaccording to another embodiment of the present invention.

FIG. 5 is a sectional diagram illustrating the transistor structureelectrically connected to pins and bonding pads by way of wire bondingaccording to another embodiment of the present invention.

FIG. 6 is a sectional diagram illustrating the transistor structureelectrically connected to pins and bonding pads by way of wire bondingaccording to another embodiment of the present invention.

FIG. 7 is a sectional diagram illustrating the transistor structureelectrically connected to pins and bonding pads by way of wire bondingaccording to another embodiment of the present invention.

FIG. 8 is a sectional diagram illustrating the transistor structureelectrically connected to pins and bonding pads by way of flip chipbonding according to an embodiment of the present invention.

FIG. 9 is a sectional diagram illustrating the transistor structureelectrically connected to pins and bonding pads by way of flip chipbonding according to another embodiment of the present invention.

FIG. 10A is a diagram illustrating an appearance of the transistorpackaging according to an embodiment of the present invention.

FIG. 10B is a diagram illustrating an appearance of the transistorpackaging according to another embodiment of the present invention.

FIG. 10C is a diagram illustrating an appearance of the transistorpackaging according to another embodiment of the present invention.

FIG. 10D is a diagram illustrating an appearance of the transistorpackaging according to another embodiment of the present invention.

FIG. 11A is a diagram illustrating an appearance of the transistorpackaging according to another embodiment of the present invention.

FIG. 11B is a diagram illustrating an appearance of the transistorpackaging according to another embodiment of the present invention.

FIG. 11C is a diagram illustrating an appearance of the transistorpackaging according to another embodiment of the present invention.

FIG. 11D is a diagram illustrating an appearance of the transistorpackaging according to another embodiment of the present invention.

FIG. 12 is a snubber circuit applied to the transistor structure of thepresent invention.

FIG. 13 is a flowchart illustrating a transistor packaging methodaccording to a first embodiment of the present invention.

FIG. 14 is a flowchart illustrating a transistor packaging methodaccording to a second embodiment of the present invention.

FIG. 15 is a flowchart illustrating a transistor packaging methodaccording to a third embodiment of the present invention.

FIG. 16 is a flowchart illustrating a transistor packaging methodaccording to a fourth embodiment of the present invention.

FIG. 17 is a flowchart illustrating a transistor packaging methodaccording to a fifth embodiment of the present invention.

FIG. 18 is a flowchart illustrating a transistor packaging methodaccording to a sixth embodiment of the present invention.

FIG. 19 is a diagram illustrating a conventional snubber circuit.

DETAILED DESCRIPTION

Detailed description of technical features and embodiments of thepresent invention would be obtained in the following description withreference to accompanying figures.

Please refer to FIG. 1A, which is a diagram illustrating a transistorstructure according to a first embodiment of the present invention. Thetransistor structure of the present invention includes a chip package 1and two pins 2 and 3, wherein the chip package 1 includes a transistordie 11 and a molding compound 12 encapsulating the transistor die 11;and the pin 2 is electrically connected to a first bonding pad 111 and asecond bonding pad 112 of the transistor die 11, and the pin 3 iselectrically connected to a third bonding pad 113 of the transistor die11.

The transistor die 11 of the transistor structure of the presentinvention is a Bipolar Junction Transistor (BJT) die, and the BJT may bean NPN type BJT die or a PNP type BJT die. Please refer to FIG. 1 inconjunction with FIG. 2A and FIG. 2B. The first bonding pad 111 of thetransistor die 11 is an emitter bonding pad, and the second bonding pad112 is a base bonding pad, and the third bonding pad 113 is a collectorbonding pad, wherein the emitter bonding pad and the base bonding padare electrically connected to the pin 2, and the collector bonding padis electrically connected to the pin 3.

Thus, base and emitter of the BJT of this embodiment are conductive, andthe transistor structure has characteristics like fast turn-on, longstorage time, switching smoothly, and small base-collector junctioncapacitance C_(bc) according to at least one junction characteristicbetween the base and the collector of the BJT die. The transistorstructure therefore may be used as a fast diode for a snubber circuit.

The snubber circuit may have one of the following structures: (1) a CBsnubber circuit, implemented by connecting the pin 2 or the pin 3 ofthis embodiment to a terminal of a capacitor to thereby form a snubbercircuit to be connected to an active component or a load in parallel(not shown); (2) a ZCB snubber circuit, implemented by connecting thepin 2 or the pin 3 of the transistor structure Q to a terminal of acapacitor C and a terminal of a zener diode D, and connecting anotherterminal of the capacitor C to another terminal of the zener diode D tothereby form a snubber circuit (as shown in FIG. 12) to be connected toan active component or a load in parallel (not shown); (3) an RCBsnubber circuit, implemented by connecting the pin 2 or the pin 3 of thetransistor structure of this embodiment to a terminal of a resistor andconnecting another terminal of the resistor to a terminal of a capacitorto thereby form a snubber circuit to be connected to an active componentor a load in parallel (not shown).

The active component is or is assembled by a Metal Oxide SemiconductorField Effect Transistor (MOSFET), a diode, a Bipolar Junction Transistor(BJT), an Insulated Gate Bipolar Transistor (IGBT), a Static InductionTransistor (SIT), or a thyristor. The load is or is assembled by aninductor, a resistor, or a capacitor. For example, the snubber circuitis connected to a primary side of a transformer of a switching powersupply in parallel and then connected to a MOSFET in series; or thesnubber circuit is connected to a secondary side of a transformer of aswitching power supply and a MOSFET in parallel; or the snubber circuitis connected to a MOSFET in parallel and then connected to a secondaryside of a transformer of a switching power supply in series to absorbspikes or noise generated by the active component while the activecomponent is switching at the high frequency. In this way, the spikesgenerated by the active component could be reduced and thus theefficiency is improved.

Please refer to following Table 1 and Table 2. Table 1 is anexperimental testing report of a conventional RCD snubber circuit, andTable 2 is an experimental testing report of the transistor structureapplied to the above mentioned RCB snubber circuit according to thisembodiment, where the RCD snubber circuit and the RCB snubber circuitare both connected to a primary side of a transformer in parallel andthen connected to a MOSFET in series. According to the testing result ofTable 1 and Table 2, the efficiency of the RCB snubber circuit of thisembodiment is proved to be better than the efficiency of theconventional RCD snubber circuit based on the experiment, especiallywhen the snubber circuit is electrically connected to a light load. Thelight load indicates that the percent of rated load is smaller or equalto 20%, namely the load accounts for less than 20%, for instance, thepercent of rated load is 1%-20%; the efficiency of Table 2 (RCB snubbercircuit) is 10.57% (57.48%-68.59%) higher than the efficiency of Table 1(RCD snubber circuit) at a condition that the percent of rated load ofboth Table 1 and Table 2 is 1%. And the efficiency of Table 2 is 1.23%(88.22%-89.45%) higher than the efficiency of Table 1 at a conditionthat the percent of rated load of both Table 1 and Table 2 is 20%.

TABLE 1 Input_Voltage (V) = 90 Vac Load_(—) Percent_of_Rated_Load 1% 2%3% 4% 5% 6% 7% 20% 25% 50% 75% 100% Output_Current (A) 0.013 0.02590.0516 0.0777 0.1038 0.1298 0.1557 0.4608 0.576 1.158 1.727 2.302Output_Voltage (V) 19.265 19.262 19.26 19.257 19.257 19.257 19.255 19.2419.232 19.2 19.19 19.14 Efficiency_(%) 57.84% 68.15% 74.17% 77.93%80.60% 81.15% 83.05% 88.22% 88.48% 89.15% 88.61% 87.94%Average_Efficiency_(%) — 88.55%

TABLE 2 Input_Voltage (V) = 90 Vac Load_(—) Percent_of_Rated_Load 1% 2%3% 4% 5% 6% 7% 0% 5% 50% 75% 100% Output_Current (A) 0.013 0.0256 0.05160.0777 0.1038 0.1298 0.1558 0.46 0.575 1.1506 1.7262 2.303Output_Voltage (V) 19.257 19.257 19.255 19.252 19.25 19.25 19.247 19.23219.227 19.192 19.16 19.13 Efficiency_(%) 68.59% 78.5% 83.42% 84.99%86.13% 86.76% 87.68% 89.45% 89.52% 89.04% 88.67% 88.11%Average_Efficiency_(%) — 88.84%

Thus, compared to the conventional RCD snubber circuit, the efficiencyof the RCB snubber circuit of the present embodiment is improved whenthe load is a light load. The snubber circuit 300A of this embodimentnot only has a dramatic improvement in efficiency, according toAverage_Efficiency in Table 1 and Table 2, there is also a slightincrease on the average efficiency by 0.3% when the load is a heavyload. Therefore, compared to using the power supply of an RCD snubbercircuit, using a power supply with the transistor structure of thepresent invention is more efficient, particularly in a light loadcondition.

Please refer to FIG. 1B, which is a diagram illustrating a transistorstructure according to a second embodiment of the present invention. Thetransistor structure of the present invention includes a chip package 1and two pins 2 and 3, wherein the chip package 1 includes a transistordie 11, a capacitor die 13, and a molding compound 12 encapsulating thetransistor die 11 and the capacitor die 13. The third bonding pad 113 ofthe transistor die 11 is electrically connected to a first bonding pad131 of the capacitor die 13. The pin 2 is electrically connected to afirst bonding pad 111 and the second bonding pad 112 of the transistordie 11, and the pin 3 is electrically connected to a second bonding pad132 of the capacitor die 13. The transistor structure of this embodimentmay make the first bonding pad 111 (or the second bond 112) of thetransistor die 11 electrically connected to the first bonding pad 131 ofthe capacitor die 13, may make the pin 2 electrically connected to thesecond bonding pad 132 of the capacitor die 13, and may make the pin 3electrically connected to the third bonding pad 113 (not shown) of thetransistor die 11. However, this is not meant to be a limitation of thepreset invention. Please refer to FIG. 2C, which shows that thetransistor die 11 of this embodiment is a BJT die, where the BJT die maybe an NPN type BJT die or a PNP type BJT die.

Thus, base and emitter of the BJT of this embodiment are conductive, andthe transistor structure has characteristics like fast turn-on, longstorage time, switching smoothly, and small base-collector junctioncapacitance C_(bc) according to at least one junction characteristicbetween the base and the collector of the BJT die. The transistorstructure may be used as a fast diode, and forms a CB snubber circuit byan electrical connection with the capacitor die. Hence, the transistorstructure could simplify the process, reduce size, and increase thewithstanding voltage when employed on packaging and applicationcircuits. The CB snubber circuit may be connected to an active componentor a load (not shown) in parallel, wherein the active component is or isassembled by a Metal Oxide Semiconductor Field Effect Transistor(MOSFET), a diode, a Bipolar Junction Transistor (BJT), an InsulatedGate Bipolar Transistor (IGBT), a Static Induction Transistor (SIT), or,a thyristor, and the load is or is assembled by an inductor, a resistor,or a capacitor. For example, the CB snubber circuit is connected to aprimary side of a transformer of a switching power supply in paralleland then connected to a MOSFET in series to absorb spikes or noisegenerated by the active component while the active component isswitching at the high frequency. Therefore, the spikes generated by theactive component could be reduced and thus the efficiency is improved.

The chip package 1 of the transistor structure of this embodiment mayinclude a resistor die, which is connected between the transistor die 11and the capacitor die 13. That is to say, the first bonding pad of theresistor die is electrically connected to the first bonding pad 111 orthe third bonding pad 113 of the transistor die 11, and the secondbonding pad of the resistor die is electrically connected to the firstbonding pad 131 (not shown) of the capacitor die 13, and the resistordie is encapsulated by the molding compound 12 to make the transistorstructure form a RCB snubber circuit. Thus, the transistor structurecould simplify the process, reduce size, and increase the withstandingvoltage when employed on packaging and application circuits.

Please refer to FIG. 1C, which is a diagram illustrating the transistorstructure according to a third embodiment of the present invention. Thetransistor structure of the present invention includes a chip package 1and two pins 2 and 3, wherein the chip package 1 includes a transistordie 11, a capacitor die 13, a zener diode die 14, and a molding compound12 encapsulating the transistor die 11, the capacitor die 13, and thezener diode die 14. The third bonding pad 113 of the transistor die 11is electrically connected to a first bonding pad 131 of the capacitordie 13 and a first bonding pad 141 of the zener diode die 14. The pin 2is electrically connected to a first bonding pad 111 and the secondbonding pad 112 of the transistor die 11, and the pin 3 is electricallyconnected to a second bonding pad 132 of the capacitor die 13 and asecond bonding pad 142 of the zener diode die 14. The transistorstructure of this embodiment may make the first bonding pad 111 and thesecond bonding pad 112 of the transistor die 11 electrically connectedto the first bonding pad 131 of the capacitor die 13 and the firstbonding pad 141 of the zener diode die 14, may make the pin 2electrically connected to the second bonding pad 132 of the capacitordie 13 and the second bonding pad 142 of the zener diode die 14, and maymake the pin 3 electrically connected to the third bonding pad 113 ofthe transistor die 11.

That is to say that, the aforesaid zener diode die 14 is electricallyconnected to the capacitor die 13 in parallel and then connected to thetransistor die 11 in series. However, this is not meant to be alimitation of the preset invention. The second bonding pad 142 of thezener diode die 14 of this embodiment may be electrically connected tothe first bonding pad 111 or the third bonding pad 113 of the transistordie 11, that is to say, the zener diode die 14 may be connected to thetransistor die 11 in parallel, and then connected to the capacitor die13 in series. Please refer to FIG. 2D, which shows that the transistordie 11 of this embodiment is a BJT die, where the BJT die may be an MPNtype BJT or a PNP type BJT die.

Thus, base and emitter of the BJT of this embodiment are conductive, andthe transistor structure has characteristics like fast turn-on, longstorage time, switching smoothly, and small base-collector junctioncapacitance C_(bc) according to at least one junction characteristicbetween the base and the collector of the BJT die. The transistorstructure may be used as a fast diode, and forms a ZCB snubber circuit(as shown in FIG. 12) by electrical connections with the capacitor dieand the zener diode die. Hence, the transistor structure could simplifythe process, reduce size, and increase the withstanding voltage whenemployed on packaging and application circuits. The ZCB snubber circuitmay be connected to an active component or a load (not shown) inparallel, wherein the active component is or is assembled by a MetalOxide Semiconductor Field Effect Transistor (MOSFET), a diode, a BipolarJunction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT),a Static Induction Transistor (SIT), or a thyristor, and the load is oris assembled by an inductor, a resistor, or a capacitor. For example,the ZCB snubber circuit is connected to a primary side of a transformerof a switching power supply in parallel and then connected to a MOSFETin series to absorb spikes or noise generated by the active componentwhile the active component is switching at the high frequency. In thisway, the spikes generated by the active component could be reduced andthus the efficiency is improved.

In addition, please refer to FIG. 3-FIG. 7, which are sectional diagramsillustrating the transistor structure electrically connected to pins andbonding pads by way of wire bonding according to embodiments of thepresent invention. The transistor structure includes a chip package 1and two pins 2 and 3, wherein the chip package 1 includes a transistordie 11, a molding compound 12, an adhesion layer 16, a die pad 17, and aplurality of bonding wires 151, 152, and 153. The chip package 1 iselectrically connected to the pin 2 and 3 by means of bonding wires 151,152, and 153 electrically connected to the first bonding pad 111, thesecond bonding pad 112, the third bonding pad 113. The pins 2 and 3 mayset at least a contact (not shown) respectively for electricallyconnecting the bonding wires 151, 152, and 153. The transistor die 11 isset on the die pad 17 by the adhesion layer 16, and the transistor die11, the adhesion layer 16, the die pad 17, the bonding wires 151, 152,153, and part of the pins 2 and 3 are encapsulated by the moldingcompound 12, therefore part of the pins 2 and 3 are embedded in themolding compound 12, and one end of each of the pins 2 and 3 is outsidethe molding compound 12. The bonding wires 151, 152, and 153 may be goldwires or made by other conductive material, the adhesion layer 16 may bea silver paste or made by other conductive paste, and the material ofthe molding compound 12 may be Epoxy or other macromolecule material.

Please refer to FIG. 3, two terminals of the bonding wire 151 of thisembodiment are electrically connected to the pin 2 and the secondbonding pad 112, and two terminals of the bonding wire 152 areelectrically connected to the pin 2 and the first bonding pad 111.Consequently, there is a short circuit between the first bonding pad 111and the second bonding pad 112. Two terminals of the bonding wire 153are electrically connected to the pin 3 and the third bonding pad 113.In addition, the pins 2 and 3 are set at two sides of the moldingcompound 12 and extend horizontally, such that the pins 2 and 3 areparallel to the die pad 17. The appearance of the packaging of thetransistor structure may be one of the appearances shown in FIG.10A-FIG. 10D, wherein the shape of the molding compound 12 may becylindrical, semicircular, or tablet-shaped, and the pins 2 and 3 may bea long lead, a short lead, lead-free, or other contact type.

Please refer to FIG. 4. Two terminals of the bonding wire 151 areelectrically connected to the pin 2 and the second bonding pad 112, andtwo terminals of the bonding wire 152 are electrically connected to thepin 2 and the first bonding pad 111. Consequently, there is a shortcircuit between the first bonding pad 111 and the second bonding pad112. Two terminals of the bonding wire 153 are electrically connected tothe pin 3 and the third bonding pad 113. In addition, the pins 2 and 3are set at two sides of the molding compound 12 and extend downward,such that the pins 2 and 3 are perpendicular to the die pad 17. Theappearance of the packaging of the transistor structure may be one ofthe appearances shown in FIG. 11A-FIG. 11D, wherein the shape of themolding compound 12 may be cylindrical, semicircular, or tablet-shaped,and the pin 15 may be a long lead, a short lead, lead-free, or othercontact type.

Please refer to FIG. 5. Two terminals of the bonding wire 151 areelectrically connected to the first bonding pad 111 and the secondbonding pad 112, resulting in a short circuit between the first bondingpad 111 and the second bonding pad 112. Two terminals of the bondingwire 152 are electrically connected to the pin 2 and the first bondingpad 111, and two terminals of the bonding wire 153 are electricallyconnected to the pin 3 and the third bonding pad 113. In addition, thepins 2 and 3 are set at two sides of the molding compound 12 and extendhorizontally, such that the pins 2 and 3 are parallel to the die pad 17.

Please refer to FIG. 6. Two terminals of the bonding wire 151 areelectrically connected to the first bonding pad 111 and the secondbonding pad 112, resulting in a short circuit between the first bondingpad 111 and the second bonding pad 112. Two terminals of the bondingwire 152 are electrically connected to the pin 2 and the bonding wire151, and two terminals of the bonding wire 153 are electricallyconnected to the pin 3 and the third bonding pad 113.

Please refer to FIG. 7. This embodiment has a short circuit between thefirst bonding pad 111 and the second bonding pad 112 by a fourth bondingpad 114 electrically connected to the first bonding pad 111 and thesecond bonding pad 112. Two terminals of the bonding wire 152 areelectrically connected to the pin 2 and the fourth bonding pad 114, andtwo terminals of the bonding wire 153 are electrically connected to thepin 3 and the third bonding pad 113.

Please refer to FIG. 8 in conjunction with FIG. 9. FIG. 8 and FIG. 9 aresectional diagrams illustrating the transistor structure electricallyconnected to pins and bonding pads by way of flip chip bonding accordingto embodiments of the present invention. The transistor structureincludes a chip package 1 and two pins 2 and 3, wherein the chip package1 includes a transistor die 11, a molding compound 12, and a bondingmaterial 18. The bonding material 18 is first formed on the surface of afirst bonding pad 111 and a second bonding pad 112. Next, the transistordie 11 is flipped over, and the first bonding pad 111, the secondbonding pad 112, and the third bonding pad 113 are connected to the pin2 and 3 through the bonding material 18, thereby making the transistordie 11 electrically connected to the pins 2 and 3. The pins 2 and 3 mayset at least a contact (not shown) respectively for electricallyconnecting the bonding material 18. The transistor die 11, the bondingmaterial 18, and part of the pins 2 and 3 are encapsulated by themolding compound 12. Therefore, part of the pins 2 and 3 are embedded inthe molding compound 12, and one end of each of the pins 2 and 3 isoutside the molding compound 12. The material of the bonding material 18may be tin or other metal material.

As shown in FIG. 8, the bonding material 18 of this embodiment includesa first bonding material 181, a second bonding material 182, and a thirdbonding material 183. The first bonding material 181 electricallyconnects the pin 2 to the third bonding pad 113. The second bondingmaterial 182 and the third bonding material 183 electrically connect thepin 3 to the first bonding pad 111 and the second bonding pad 112.Consequently, there is a short circuit between the first bonding pad 111and the second bonding pad 112.

As shown in FIG. 9, the bonding material 18 of this embodiment includesa first bonding material 181 and a fourth bonding material 184. Thefirst bonding material 181 electrically connects the pin 2 to the thirdbonding pad 113. The fourth bonding material 184 electrically connectsthe pin 3 to the first bonding pad 111 and the second bonding pad 112.Consequently, there is a short circuit between the first bonding pad 111and the second bonding pad 112.

Please refer to FIG. 3 in conjunction with FIG. 13. FIG. 13 is aflowchart of a transistor packaging method according to a firstembodiment of the present invention. The transistor packaging methodincludes following steps: first, providing a transistor die 11 having afirst bonding pad 111, a second bonding pad 112, and a third bonding pad113 (S100); then, forming a bonding wire 151 and a bonding wire 152 onthe surfaces of the first bonding pad 111 and the second bonding pad112, respectively, and electrically connecting the bonding wires 151,152 to a first pin 2 (S102); then, forming a bonding wire 153 on thesurface of the third bonding pad 113, and electrically connecting thebonding wire 153 to a second pin 3 (S104); finally, providing a moldingcompound 12 encapsulating the transistor die 11, the bonding wires151-153, and part of the pins 2 and 3 (S106).

Please refer to FIG. 5 in conjunction with FIG. 14. FIG. 14 is aflowchart of a transistor packaging method according to a secondembodiment of the present invention. The transistor packaging methodincludes following steps: first, providing a transistor die 11 having afirst bonding pad 111, a second bonding pad 112, and a third bonding pad113 (S200); then, forming a bonding wire 151 on the surface of the firstbonding pad 111 and electrically connecting the bonding wire 151 to thesecond bonding pad 112 (S202); then, forming a bonding wire 152 on thesurface of the first bonding pad 111 or the second bonding pad 112, andelectrically connecting the bonding wire 152 to a first pin 2 (S204);then, forming a bonding wire 153 on the surface of the third bonding pad113 and electrically connecting the wire 153 to a second pin 3 (S206);finally, providing a molding compound 12 encapsulating the transistordie 11, the wires 151-153, and part of the pins 2 and 3 (S208).

Please refer to FIG. 6 in conjunction with FIG. 15. FIG. 15 is aflowchart of a transistor packaging method according to a thirdembodiment of the present invention. The transistor packaging methodincludes following steps: first, providing a transistor die 11 having afirst bonding pad 111, a second bonding pad 112, and a third bonding pad113 (S300); then, forming a bonding wire 151 on the surfaces of thefirst bonding pad 111 and electrically connecting the bonding wire 151to the second bonding pad 112 (S302); then, forming a bonding wire 152on the surface of a first pin 2 and electrically connecting the bondingwire 152 to the bonding wire 151 (S304); then, forming a bonding wire153 on the surface of the third bonding pad 113 and electricallyconnecting the bonding wire 153 to a second pin 3 (S306); finally,providing a molding compound 12 encapsulating the transistor die 11, thebonding wires 151-153, and part of the pins 2 and 3 (S308).

Please refer to FIG. 7 in conjunction with FIG. 16. FIG. 16 is aflowchart of a transistor packaging method according to a secondembodiment of the present invention. The transistor packaging methodincludes following steps: first, providing a transistor die 11 having afirst bonding pad 111, a second bonding pad 112, and a third bonding pad113 (S400); then, forming a fourth bonding pad 114 on the surface of thefirst bonding pad 111, the second bonding pad 112, and the third bondingpad 113, and electrically connecting the fourth bonding pad 114 to thefirst bonding pad 111 and the second bonding pad 112 (S402); then,forming a bonding wire 152 on the surface of the fourth bonding pad 114and electrically connecting the bonding wire 152 to a first pin 2(S404); then, forming a bonding wire 153 on the surface of the thirdbonding pad 113 and electrically connecting the bonding wire 153 to asecond pin 3 (S406); finally, providing a molding compound 12encapsulating the transistor die 11, the fourth bonding pad 114, thebonding wires 152 and 153, and part of the pins 2 and 3 (S408).

Please refer to FIG. 8 in conjunction with FIG. 17. FIG. 17 is aflowchart of a transistor packaging method according to a fifthembodiment of the present invention. The transistor packaging methodincludes following steps: first, providing a transistor die 11 having afirst bonding pad 111, a second bonding pad 112, and a third bonding pad113 (S500); then, forming a first bonding material 182 and a secondbonding material 183 on the surfaces of the first bonding pad 111 andthe second bonding pad 112, respectively, and electrically connectingthe first bonding material 182 and the second bonding material 183 to afirst pin 2 (S502); then, forming a third bonding material 183 on thesurface of the third bonding pad 113 and electrically connecting thethird bonding material 183 to a second pin (S504); finally, providing amolding compound 12 encapsulating the transistor die 11, the bondingmaterial 18, and part of the pins 2 and 3 (S506).

Please refer to FIG. 9 in conjunction with FIG. 18. FIG. 18 is aflowchart of a transistor packaging method according to a secondembodiment of the present invention. The transistor packaging methodincludes following steps: first, providing a transistor die 11 having afirst bonding pad 111, a second bonding pad 112, and a third bonding pad113 (S600); then, forming a fourth bonding material 184 on the surfacesof the first bonding pad 111 and the second bonding pad 112,respectively, and electrically connecting the fourth bonding material184 to a first pin 2 (S602); then, forming a first bonding material 181on the surface of the third bonding pad 113 and electrically connectingthe first bonding material 181 to a second pin (S604); finally,providing a molding compound 12 encapsulating the transistor die 11, thebonding material 181 and 184, and part of the pins 2 and 3 (S606).

The transistor dies of the aforesaid embodiments of the transistorpackaging method are BJT dies.

In summary, according to the above disclosed embodiments, the presentinvention actually can achieve the desired objective by using one pinelectrically connected to a first bonding pad and a second bonding padof the transistor die, and another pin electrically connected to a thirdbonding pad of the transistor die. The transistor structure may beemployed in a snubber circuit, or the snubber circuit may beencapsulated in the two-pin transistor structure to connect an activecomponent or a load in parallel to absorb spikes or noise generated bythe active component while the active component is switching at a highfrequency. Therefore, the packaging of the transistor structure couldsimplify the process, reduce size, increase the withstanding voltage,and improve the efficiency and reduce the spike voltage of the powersupply of the snubber circuit. The present invention indeed haspractical value undoubtedly, and therefore has the utility which is newand non-obvious over the conventional designs.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A transistor structure, comprising: a chip package, comprising atransistor die and a molding compound encapsulating the transistor die;and two pins, wherein a first pin is electrically connected to a firstbonding pad and a second bonding pad of the transistor die, and a secondpin is electrically connected to a third bonding pad of the transistordie.
 2. The transistor structure of claim 1, wherein the chip packagefurther comprises: a capacitor die, wherein a first bonding pad of thecapacitor die is electrically connected to the first bonding pad or thethird bonding pad of the transistor die, a second bonding pad of thecapacitor die is electrically connected to the first pin or the secondpin, and the molding compound further encapsulates the capacitor die. 3.The transistor structure of claim 2, wherein the chip package furthercomprises: a zener diode die, wherein a first bonding pad of the zenerdiode die is electrically connected to the first bonding pad of thecapacitor die and the first bonding pad or the third bonding pad of thetransistor die, a second bonding pad of the zener diode die iselectrically connected to the second bonding pad of the capacitor die orthe first bonding pad or the third bonding pad of the transistor die,and the molding compound further encapsulates the zener diode die. 4.The transistor structure of claim 2, wherein the chip package furthercomprises: a resistor die, wherein a first bonding pad of the resistordie is electrically connected to the first bonding pad or the thirdbonding pad of the transistor die, a second bonding pad of the resistordie is electrically connected to the first bonding pad of the capacitordie, and the molding compound further encapsulates the resistor die. 5.The transistor structure of claim 1, wherein the first pin or the secondpin of the transistor structure is connected to a terminal of acapacitor, thus forming a snubber circuit to be connected to an activecomponent or a load in parallel.
 6. The transistor structure of claim 5,wherein the active component is or is assembled by a Metal OxideSemiconductor Field Effect Transistor (MOSFET), a diode, a BipolarJunction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT),a Static Induction Transistor (SIT), or a thyristor; and the load is oris assembled by an inductor, a resistor, or a capacitor.
 7. Thetransistor structure of claim 5, wherein the terminal of the capacitoris further connected to a terminal of a zener diode, and anotherterminal of the capacitor is connected to another terminal of the zenerdiode, thus forming a snubber circuit to be connected to an activecomponent or a load in parallel.
 8. The transistor structure of claim 7,wherein the active component is or is assembled by a Metal OxideSemiconductor Field Effect Transistor (MOSFET), a diode, a BipolarJunction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT),a Static Induction Transistor (SIT), or a thyristor; and the load is oris assembled by an inductor, a resistor, or a capacitor.
 9. Thetransistor structure of claim 1, wherein the first pin or the second pinis connected to a terminal of a resistor, and another terminal of theresistor is connected to a terminal of a capacitor, thus forming asnubber circuit to be connected to an active component or a load inparallel.
 10. The transistor structure of claim. 9, wherein the activecomponent is or is assembled by a Metal Oxide Semiconductor Field EffectTransistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), anInsulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor(SIT), or a thyristor; and the load is or is assembled by an inductor, aresistor, or a capacitor.
 11. The transistor structure of claim 1,wherein the transistor die is a Bipolar Junction Transistor (BJT) die.12. The transistor structure of claim 11, wherein the first bonding padof the transistor die is an emitter bonding pad, the second bonding padis a base bonding pad, and the third bonding pad is a collector bondingpad.
 13. The transistor structure of claim 1, wherein the first bondingpad, the second bonding pad, and the third bonding pad are connected tothe pins through wire bonding.
 14. The transistor structure of claim 13,wherein the wire bonding includes three bonding wires connected to thepins respectively.
 15. The transistor structure of claim 13, wherein thefirst bonding pad and the second bonding pad are electrically connectedto each other, one of the pins is connected to the first bonding pad orthe second bonding pad through a bonding wire, and the third bonding padis connected to another of the pins through a bonding wire.
 16. Thetransistor structure of claim 13, wherein the first bonding pad iselectrically connected to the second bonding pad through a bonding wireor a bonding material.
 17. The transistor structure of claim 1, whereinthe chip package further comprises a die pad, and the transistor die isset on the die pad by an adhesion layer.
 18. The transistor structure ofclaim 1, wherein the first bonding pad, the second bonding pad, and thethird bonding pad are electrically connected to the pins through flipchip bonding.
 19. A transistor packaging method, comprising: providing atransistor die having a first bonding pad, a second bonding pad, and athird bonding pad; forming bonding wires on surfaces of the firstbonding pad and the second bonding pad, respectively, and electricallyconnecting the bonding wires to a first pin; forming a bonding wire on asurface of the third bonding pad, and electrically connecting thebonding wire to a second pin; and providing a molding compoundencapsulating the transistor die, the bonding wires, and part of thepins.
 20. A transistor packaging method, comprising: providing atransistor die having a first bonding pad, a second bonding pad, and athird bonding pad; forming a bonding material on surfaces of the firstbonding pad and the second bonding pad, and electrically connecting thebonding material on the first bonding pad and the second bonding pad toa first pin. forming a bonding material on a surface of the thirdbonding pad, and electrically connecting the bonding material on thethird bonding pad to a second pin; and providing a molding compoundencapsulating the transistor die, the bonding materials, and part of thepins.